(a) Field of the Invention
The present invention concerns parallel processors used for the simultaneous and rapid acquisition and processing of very large data assemblies, for example the data contained in a video image.
(B) Discussion of the Prior Art
A parallel type processor is generally formed of a large number of elementary processors.
Each of the elementary processors contained one or several memories with a possibility of access to one bit among P bits. These memories may be R.O.M.S. or R.A.M.s with random or sequential access. In each elementary processor, the memory is associated with a logic circuit containing one or several storage flip-flops, each able to record one bit. The logic circuit also contains means enabling a certain number of Boolean operations to be performed between the various bits stored in the flip-flops and a bit addressed in the elementary processors memory. Finally, the logic circuit contains means for transferring the result of the calculation into the memory. Such an elementary processor, or word, therefore has a structure identical to that of a classical series computer and is capable of carrying out sequentially any arithmetic, Boolean or semantic calculation between the various parts of each memory in each elementary processor, provided that it is suitably managed by the various control signals and addresses which are addressed in common to all the words of the processor as a whole or of a parallel processor.
A parallel processor designed in this way can therefore perform the same calculation simultaneously in all the words and this, with identical memory addresses. Certain data may be common to all the elementary processors and, in this case, they may be transferred by the channel used for the various control signals. Hence, any operation of comparison or search equal to a common value can be carried out simultaneously on all the elementary processors. These data can also be different if the contents of the memories are used such as they are, i.e. the calculation is then carried out between two data in the very memory of each word.
In parallel processors, relatively slow memories are generally used. Therefore, to increase the speed of data processing, an attempt is made to perform several calculations simultaneously in the logic circuit of each word by providing a larger number of storage flip-flops, so that several Boolean operations can be performed in parallel between the data contained in these flip-flops and those withdrawn from the memories.
However, such an arrangement of each elementary processor only allows the processing speed to be increased in a limited way or, in other terms, the processing speed depends on the number of flip-flop circuits used, a high speed requiring a very large number of flip-flops and therefore being excessively expensive.